1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor structures, and more particularly, to the fabrication of doped crystalline silicon (polysilicon) regions or lines used, for example, as gate electrodes in field effect transistors.
2. Description of the Related Art
Feature sizes of integrated circuits, such as CMOS (complementary metal-oxide semiconductor) transistors are steadily scaled into the deep-submicron regime for higher integration density and performance. The scaling of critical dimensions, such as the gate length of a field effect transistor, may, however, entail significant changes of related features, and of respective process sequences for manufacturing these features, in order to not unduly offset the advantages obtained by reducing the critical dimensions. For example, upon reducing the gate length and, thus, the channel length of a field effect transistor, thinner gate dielectrics, i.e., gate insulation layers separating the gate electrode from the channel region, are required to provide sufficient current drive capability since the supply voltage is also to be scaled down.
Generally, the desired high performance of these modem CMOS devices requires maximizing the inversion charge formed in the channel region under the control of a voltage applied to the gate electrode and the drive current of the device. To achieve this effect, it is necessary to maximize the capacitive coupling between the gate electrode, usually formed of polysilicon, and the channel formed adjacent to the gate insulation layer. This is generally accomplished, as pointed out above, by thinning the gate insulation layer that separates the channel from the gate electrode. In sophisticated integrated circuits that include transistor elements with a gate length of 0.25 μm or even less, ultra-thin dielectrics with a thickness of less than 2 nm may be required as gate insulation layers to ensure the required drive current capability. Reducing the thickness of the gate insulation layer, however, involves a significant increase of leakage currents through the gate insulation layer.
A further characteristic influencing the effective gate capacitance is associated with the capacitive component of a depletion layer in the gate electrode, which forms when the gate electrode is biased to form an inversion layer in the channel. Generally, the gate electrode is heavily doped to increase the conductivity of the gate electrode, and the depletion layer is caused by the reduced dopant concentration that is created during the implant of the dopants and the subsequent anneal cycles for diffusing the dopants and curing crystal damage, since the strict process requirements for sophisticated semiconductor devices do not allow a desired high and uniform dopant concentration to be obtained throughout the entire gate electrode. Especially in deep-submicron devices, the contribution of a large depletion layer may overcompensate the effect achieved by thinning the gate insulation layer, and the resulting device may, therefore, suffer from a reduced capacitive coupling. Due to the exponential increase of the associated leakage currents in transistors with a thin gate insulation layer, it may, therefore, be important to keep the depletion layer of the gate electrode as small as possible.
The depletion layer may successfully be minimized by increasing the doping level of the gate electrode. However, in case of PMOS (P-channel metal-oxide semiconductor) devices having boron-doped gate electrodes, an increased doping level of the gate electrode is typically associated with a penetration of boron through the gate insulation layer. The penetration of boron results in a degradation of the reliability of the gate insulation layer owing to damage caused by the boron atoms. Moreover, a shift of the threshold voltage (VT) may occur due to the altered doping levels in the channel. This is especially true for thin gate dielectrics with a thickness of less than 4 nm. With such thin gate insulation layers, the gate-depletion effect and boron penetration are critical and place severe constraints on the doping and the annealing conditions of the gate electrode.
To deal with the problem of boron penetration, it has been suggested to fill the polysilicon grain boundaries, which serve as the main diffusion path, with nitrogen. For an effective barrier to reduce the gate depletion layer, it is necessary to place a high dose of nitrogen close to the interface of the polysilicon gate electrode and the gate insulation layer. Typically, the nitrogen is ion implanted and implant energies on the order of several kilo-electron volts (keV) are required. This ion implant conventionally suffers from the problem that either nitrogen atoms penetrate into the channel where they reduce the carrier mobility and tend to reduce the device reliability, or that the nitrogen peak concentration is located too far from the interface between the polysilicon gate electrode and the gate insulation layer, thereby creating a relatively wide depletion layer.
In order to illustrate the problems discussed above in more detail, a typical prior art processing sequence for the manufacture of a PMOS transistor is described with reference to FIGS. 1a-1c and FIG. 2. For convenience, only the process steps relevant for the present invention are shown.
FIG. 1a schematically shows a cross-sectional view of a semiconductor structure 100 comprising a substrate 101 with shallow trench isolation (STI) regions 112 formed therein, which define an active region, which will be referred to as N-well 110, in and over which a P-channel transistor is to be formed. A gate insulation layer 114 is formed on the substrate 101 with a layer of polysilicon 116 formed on the gate insulation layer 114. Forming the STI regions 112 followed by a plurality of implantation steps for defining the N-well 110, the growth or deposition of the gate insulation layer 114 and the deposition of the polysilicon layer 116 are carried out by well-established processes and will not be described in detail herein.
FIG. 1b shows the semiconductor structure 100 during an implant process 118 for introducing nitrogen either in atomic or molecular form (N14 or N28) into the polysilicon layer 116. Typically, implant energies of several keV are used to implant the nitrogen, wherein the localization of a peak concentration of nitrogen within the polysilicon layer 116 is difficult to be controlled, as will be discussed in more detail below with reference to FIG. 2.
FIG. 1c shows the semiconductor structure 100 with a PMOS transistor 120 formed in and on the N-well 110. The completed PMOS transistor 120 includes a source region 123 and a drain region 124, a portion of the gate insulation layer, denoted by 114a, a gate electrode 126, and a sidewall spacer 128. The shading of the gate electrode 126 indicates the local nitrogen concentration arising from the nitrogen implant 118, which can be seen clearer in the graph of FIG. 2.
FIG. 2 schematically shows the nitrogen concentration represented by curves 230, 232 and 234, respectively, on the ordinate versus the depth z on the abscissa, for three different implant energies, taken along the line 122 of FIG. 1c. A depth of z=0 corresponds to the top surface 129 of the gate electrode 126. The relatively high energies associated with conventional ion implantation represent a significant challenge with respect to accurate positioning of the nitrogen peak concentration within the polysilicon layer 116 and, thus, within the gate electrode 126, since the depth distribution of the nitrogen atoms depends on the initial implantation energy.
In order to obtain a desired high concentration of dopants for improving the conductivity of the gate electrode 126 even in the vicinity of the gate insulation layer 114a, it is necessary to place the location of the peak concentration of nitrogen acting as a diffusion barrier as closely as possible to the gate insulation layer 114a. Curve 234 represents a nitrogen depth distribution having its peak concentration, or at least a relatively high nitrogen concentration, close to the gate insulation layer 114a. Due to the wide variation in the depth direction of the implanted nitrogen ions, the amount of nitrogen ions penetrating through the gate insulation layer 114a into the N-well 110 is drastically increased as the peak is placed relatively close to the gate insulation layer 114a. This penetration may severely affect the quality of the (very thin) gate insulation layer 114a, thereby reducing device reliability, and may also result in reduced transistor performance owing to a reduced carrier mobility in the N-well 110. If, on the other hand, the nitrogen peak is placed sufficiently far away from the gate insulation layer 114a to substantially avoid nitrogen penetration into and through the gate insulation layer 114a, as illustrated by curve 230, the boron dopants will be blocked too far from the gate insulation layer 114a, thereby creating a lightly doped zone between the peak position and the gate dielectric, which in turn leads to a severe gate depletion during transistor operation, thereby reducing the capacitive coupling between the channel and the gate electrode 126 and, thus, decreasing the current drive capability of the transistor 120.
In the conventional implantation process, it may, thus, be extremely difficult to establish an implantation scheme so as to place a sufficiently high nitrogen dose close enough to the gate insulation layer 114a without causing severe reliability and performance degradation, as is represented by curve 232. Thus, in conventional processing, the intricacy to achieve a satisfactory distribution is associated with the difficulty to accurately position the peak concentration of the nitrogen distribution close to the gate insulation layer 114a without unduly penetrating it.
In view of the above explained problems, a need exists for a an improved semiconductor device in which a desired dopant concentration may be obtained within a specified device region without unduly affecting an adjacent region.